1. Field of the Invention
The present invention relates to an impedance control circuit of a semiconductor device for matching impedance between the output driver of the semiconductor device and an external system.
2. Description of the Related Art
Typically, semiconductor devices are mounted on a Printed Circuit Board (PCB). The PCB serves as a medium for transmitting data in the semiconductor devices to an external system. If there is an impedance mismatch between the PCB and the semiconductor devices when data from the semiconductor devices is output to the PCB, the data is distorted.
Conventionally, a predetermined external resistor is generally connected to a semiconductor device to match the output impedance of an output driver with the input impedance of a transmission medium such as a PCB. In some instances, an impedance control circuit is additionally included in the semiconductor device to adjust the output impedance of the output driver.
FIG. 1 is a block diagram of a conventional impedance control circuit. Referring to FIG. 1, the impedance control circuit includes a first resistor R1, a second resistor R2, two low-pass filters 101 and 103, a comparator (COM) 105, a flip-flop 107, a ring oscillator (R/O) 109, an impedance adjustment circuit 111, and an up/down (U/D) counter 113. In, the impedance adjustment circuit 111, a plurality of transistors 1111 through 1115 that have gates with a different width-to-length (W/L) ratio are connected in parallel. The gates of a plurality of transistors 1111 through 1115 are opened or closed according to signals of the U/D counter 113.
The impedance control circuit is generally built in the interior (inside the dotted line) of the semiconductor device and operates in response to an external resistor (Rex) installed outside the semiconductor device (outside the dotted line) by a user.
A method for operating the conventional impedance control circuit is described below.
The first resistor R1 and the second resistor R2 are connected in series between a power supply voltage Vcc and ground voltage GND. The level of a reference voltage Vref depends on the ratio of resistance between the first resistor R1 and the second resistor R2. The external resistor Rex is connected to a pin 115 of the semiconductor device and a target voltage Vtarget is output at pin 115.
Generally, at the circuit nodes having the reference voltage Vref and the target voltage Vtarget, high frequency noise is present. The noise can be removed passing the signals at these nodes through the low-pass filters 101 and 103, respectively. The comparator 105 compares the difference, between the reference voltage Vref and the target voltage Vtarget. The compared result is saved in the flip-flop 107 which is operated in response to a signal output from the ring oscillator 109.
The U/D counter 113 receives the result saved in the flip-flop 107 and generates a plurality of control signals that control the gates of the transistors 1111 through 1115 included in the impedance adjustment circuit 111. The target voltage Vtarget is adjusted by opening or closing the transistors 1111 through 1115 in accordance with the control signals generated by the U/D counter 113.
All of the output ports of the semiconductor device that are compatible to the system""s configuration and should support the target voltage Vtarget. Therefore, the control signals of the U/D counter 113 are transferred to an output driving transistor included in the output port of the semiconductor device. The transferred control signals are used to open or close the output driving transistor and match the impedance with the transmission medium, e.g., the PCB.
However, the conventional impedance control circuit illustrated in FIG. 1 has disadvantages in that an external resistor Rex must be used. It is inevitable that even the predetermined precise external resistor has at least xc2x15% deviation from a target resistance value. If a plurality of external resistors are used, each with a different deviation from the target resistance value, the design of the semiconductor device in the system becomes more complicated to account for such deviations. In addition, if the external resistor need be built in the PCB, the more the semiconductor ports that use the external resistor, the more external resistors are needed. As a result, the size of the PCB is increased.
To solve the above-described problems, it is an object of the present invention to provide an impedance control circuit designed to match the impedance between a semiconductor device and a transmission medium (PCB) by using a current source installed in the semiconductor device instead of using an external resistor.
To achieve the above objective, according to an embodiment of the present invention, the impedance control circuit includes a current source, an impedance adjustment circuit, a comparator, a thermal code generator, a control circuit, and a register.
The current source is installed in the semiconductor device and regularly provides a certain level of power. The impedance adjustment circuit is connected to the current source in series and adjusts the amount of current fed by the current source in accordance with a plurality of second control signals. The comparator compares a reference voltage generated by a voltage reference circuit installed in the semiconductor device with a comparison output voltage generated at a node where the current source and the impedance adjustment circuit meet. The comparator performs the above comparison according to an operation mode signal, which determines the mode of operation of a circuit, and a clock signal.
The thermal code generator is initialized by a reset signal and receives the output signal of the comparator and the clock signal. Then, the thermal code generator outputs a plurality of first control signals corresponding to the output signal of the comparator in accordance with the clock signal. The control circuit receives the output signal from the comparator and the clock signal. Then, the control circuit counts the number of logic value transitions of the output signal of the comparator and generates a complete signal depending on the clock signal if a certain pre-defined condition is met. The register latches the first control signals in response to the complete signal and generates the second control signals.
According to an aspect of the present invention, a method and an impedance control circuit are provided, comprising:
a current source for providing a substantially constant current;
an impedance adjustment circuit connected to the current source, for adjusting the current fed by the current source in response to a plurality of second control signals and to output an output signal at a target voltage;
a comparator for comparing a reference voltage with the target voltage and outputting a compared signal;
a thermal code generator for receiving the compared signal and a clock signal and outputting a plurality of first control signals corresponding to the compared signal in response to the clock signal;
a control circuit for receiving the compared signal and the clock signal and counting the number of logic value transitions of the compared signal and for generating a complete signal in response to the clock signal to stop operating the comparator if a predetermined condition is met; and
a register for latching the first control signals in response to the complete signal and generating the second control signals.